1. Field of the Invention
This invention relates to insulated gate field effect transistor devices. In particular, it relates to a method for reducing the charges induced in the dielectric layers which overlay the active regions of the field effect transistor.
2. Description of the Prior Art
In U. S. Pat. Nos. 3,811,076, in the name of William M. Smith, Jr., and 3,841,926, in the names of Garnache et al, which are assigned to the same assignee as the present invention, there is described an integrated circuit field effect transistor structure and method, respectively, which includes a capacitor acting as a storage element. From the standpoint of cost and performance, the storage element described therein fills a need for a large capacity memory with reasonable speed but which is very inexpensive to fabricate in highly dense form in a semiconductor substrate.
A key element of the memory cell described in the above-reference patents is a conducting member disposed on an insulating layer above the semiconductor substrate. The electrode, preferably comprising polycrystalline silicon (polysilicon), is both a field relief electrode (field shield) as well as one of the electrodes of a capacitor. After the formation of this polysilicon electrode, an insulating layer of conductive silicon dioxide is also formed. The insulating layer is required because it electrically isolates the polysilicon layer from succeeding levels of metallization.
We have found, however, that a problem exists in the operation of the completed memory structure, which is due to the conductive silicon dioxide layer at the interface with the silicon nitride gate insulator and the presence of the polysilicon electrode. We use the term "conductive" silicon dioxide in a relative sense. Thus, at an oxide field of 4 .times. 10.sup.6 v/cm, the conductivity of the silicon dioxide layer formed on the polycrystalline silicon layer is about one million times greater than the conductivity of silicon dioxide formed by thermal oxidation of single crystal silicon.
The problem occurs as follows:
When a positive bias is applied to either the polysilicon field shield or to the gate electrode, electrons are extracted from the silicon nitride into the silicon dioxide layer. When, during the operation of the device, the electrons are removed, a net positive charge remains at the interface between the silicon dioxide layer and the silicon nitride layer. This charge tends to invert that area of the silicon semiconductor substrate which is below the conductive silicon dioxide layer. This inversion causes an increase in what is termed subthreshold leakage, i.e., current which tends to flow within the device at below the nominal threshold voltage of the field effect transistor. This problem has become known as the "sidewalk" problem because the inversion of the silicon occurs below two parallel strips of conductive silicon dioxide. These strips, located below the source and drain electrodes of the FET, are not controlled by the gate electrode and cause parasitic leakage.
Attempts to reduce sidewalk leakage have been made both by increasing the temperature at which the polysilicon is oxidized from 925.degree. C to 1075.degree. C as well as by delaying the diborane flow during the initial stages of the in situ boron-doped polysilicon deposition process. These attempts have had some success in reducing sidewalk leakage. However, they have not been entirely satisfactory.